Synchronous dynamic semiconductor memories with random access (SDRAM), and in particular SDRAM with double data rate (DDR-SDRAM) output, during reading out, their data (for which the abbreviation “DQ” is used) synchronously to a clock signal output by the memory. This clock signal, which is also referred to as data strobe and is usually abbreviated as “DQS”, in turn has to be synchronous to a clock signal (CLK) input externally in the memory. The external clock signal is generated by devices connected with the memory and communicating therewith and conveying the read instruction to the memory, said devices being, to facilitate matters, referred to as “system” in the following. The system may, for instance, consist of a processor. To the external clock signal CLK or the strobe signal DQS, respectively, there are simultaneously also generated respective complementary signals that are referred to as BCLK or BDQS, respectively. FIG. 1 shows an SDRAM with the above-explained non-complementary signals CLK and DQS and the data signal DQ. FIG. 2 illustrates in a time flowchart the external clock signal (CLK) with its complementary (BCLK), the data strobe (DQS) with its complementary (BDQS), and the data signal (DQ) together with the synchronization between data strobe and data signal, and the synchronization between data strobe and external clock signal.
The DDR-SDRAM-memories comprise a device for synchronizing the data strobe (DQS) generated from the external clock signal with the external clock signal (CLK), and a device for correcting the duty cycle of the clock signal predetermined by the system. The duty cycle correcting device works with the object of generating, from the external clock, a clock on the DRAM chip with a duty cycle of 0.5, even when an imprecise external clock signal exists which has a duty cycle deviating therefrom. This is because the duty cycle predetermined by the system clock frequently does not concur with the desired duty cycle of 0.5, which may, for instance, be caused by fluctuations in the supply voltage, the process temperature, or the external load of the chip. The duty cycle here means the relation between the H-level duration of the clock signal and the clock period, wherein the duty cycle, with semiconductor memories with double data rate in which one data bit is addressed with the rising clock edge and one with the falling clock edge, should have a value of 0.5, so that the time window for reading out the data, the so-called data eye, which is created by the overlapping of corresponding logic states of data strobe and data signal, becomes as large as possible and ensures a reliable reading out of the data from the memory chip to the system.
FIG. 3 illustrates a comparison between a distorted and a corrected clock signal. FIG. 3a shows an external clock signal CLK, BCLK with a distorted duty cycle larger than 50 percent since the duration of the H-level (th) exceeds the duration of the L-level (tl). FIG. 3b shows a data strobe DQS, BDQS gained from the distorted clock signal CLK, BCLK, with a duty cycle of 50 percent, wherein th=tl.
Known devices for correcting the duty cycle of a clock signal, such as they are, for instance, described in German patent application No. 102 14 304.8, consist, as a rule, of two elements, a duty cycle determining means and a duty cycle modifying means that receives an external clock signal with a particular, as a rule faulty, duty cycle, is capable of modifying the duty cycle as a function of a correction signal supplied by the duty cycle determining means, and outputs a clock signal with a corrected duty cycle which may, for instance, be used as data strobe in an SDRAM. The principle of the known devices for correcting the duty cycle is explained in FIGS. 4 and 5.
FIG. 4 shows the functioning of the duty cycle modifying means. The duty cycle modifying means receives the external clock signal CLK and delays same by means of a first delay means 1 by a certain value T1n, so that a delayed clock signal CLKA results, which is also illustrated in the time flowchart in FIG. 4 at the left bottom. Likewise, the complementary clock signal BCLK is delayed by means of a second delay means 2 by a certain value T1p, so that a delayed clock signal BCLKA results, which is also illustrated in FIG. 4 at the left bottom. The delays T1n and T1p of the two delay means 1 and 2 are variably adjustable via a correction signal supplied by the duty cycle determining means (cf. FIG. 5). The two delayed clock signals CLKA and BCLKA are fed to a duty cycle recovery means D which is also described in the above-mentioned patent application and works such that it generates a clock signal and a complementary clock signal with a corrected duty cycle (RCLK or BRCLK, respectively) by producing, with a rising edge of the clock signal CLKA, a rising edge of the clock signal RCLK and a falling edge of the clock signal BRCLK, and with a rising edge of the clock signal BCLKA, a falling edge of the clock signal RCLK and a rising edge of the clock signal BRCLK, which can be seen in FIG. 4 at the bottom. In the left portion of FIG. 4, the case where the two delay times T1n and T1p are equal is illustrated for explanation, so that the clock signals RCLK and BCLK have a duty cycle that differs from 50 percent and is thus not ideal. In FIG. 4, on the contrary, the case is illustrated in which the duty cycle determining means has found that the actual duty cycle of CLK and BCLK differs from 50 percent (i.e. 0.5), so that a correction signal was sent to the delay means, thereby modifying the delay times T1n and T1p, so that clock signals RCLK and BCLK with a modified duty cycle result, which now corresponds to the ideal value of 50 percent.
FIG. 5 illustrates the principle of a known duty cycle determining means. The determination of the duty cycle is, in particular with frequencies of e.g. 300 MHz and above, very difficult since with such high frequencies the time difference between the H-level duration th and the L-level duration t1 may be in the range of some Pico seconds. In the case of the known duty cycle determining means illustrated in FIG. 5, two controllable switches are used, one of which being controlled via the external clock signal (CLK), and the second one being controlled via the inverted external clock signal (BCLK), each of them being connected with an identical current source which may, for instance, consist of a MOS-FET. Both current sources are adapted to be connected via one of the respective switches with a capacitor.
On actuation of the switch that is actuated by an H-level of the non-inverted clock signal the capacitor is charged, and on actuation of the other switch that is actuated by an H-level of the inverted clock signal the capacitor is discharged. The voltage resulting at the capacitor after a clock period is then a measure for displacements of the duty cycle in the one or the other direction. This principle is illustrated in FIG. 5, where the first switch is designated with sA, the second switch with sB, the first current source with Ia, the second current source with Ib, the capacitor with C, the voltage at the capacitor with Vc, and the voltage at the capacitor after a clock period with Vc(Tp). As can be recognized from the time flowchart on the right in FIG. 5, the balance between charging and discharging results in a voltage at the capacitor which is a measure for a displacement of the duty cycle from the ideal value of 50 percent. This voltage may now be used as a correction signal for controlling the variable time delays of the delay means of the duty cycle modifying means illustrated in FIG. 4.
The known duty cycle determining means described in connection with FIG. 5 does, however, comprise a number of drawbacks. Thus, the current sources and switches have to be manufactured in a relatively expensive manner, i.e. by making use of a relatively large layout region, to achieve the desired exactness. Moreover, it is relatively difficult to manufacture two current sources that are exactly identical in their behavior since certain deviations result by fluctuations during the manufacturing of semiconductors. The same applies to the switches sA and sB which also have to be exactly identical. Finally, the courses of the charging and discharging curves illustrated in FIG. 5 are not exactly linear, so that further undesired deviations will result.